mmhal_wlan.h

/*
 * Copyright 2023 Morse Micro
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
 
#pragma once
 
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <time.h>
#include "mmpkt.h"
#include "mmwlan.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
 
typedef void (*mmhal_irq_handler_t)(void);
 
void mmhal_wlan_init(void);
 
void mmhal_wlan_deinit(void);
 
void mmhal_read_mac_addr(uint8_t *mac_addr);
 
void mmhal_wlan_wake_assert(void);
 
void mmhal_wlan_wake_deassert(void);
 
bool mmhal_wlan_busy_is_asserted(void);
 
void mmhal_wlan_register_busy_irq_handler(mmhal_irq_handler_t handler);
 
void mmhal_wlan_set_busy_irq_enabled(bool enabled);
 
struct mmhal_robuf
{
    const uint8_t *buf;
    uint32_t len;
    void (*free_cb)(void *arg);
    void *free_arg;
};
 
#define MMHAL_WLAN_FW_BCF_MIN_READ_LENGTH   (4)
 
void mmhal_wlan_read_bcf_file(uint32_t offset, uint32_t requested_len, struct mmhal_robuf *robuf);
 
void mmhal_wlan_read_fw_file(uint32_t offset, uint32_t requested_len, struct mmhal_robuf *robuf);
 
 
void mmhal_wlan_spi_cs_assert(void);
 
void mmhal_wlan_spi_cs_deassert(void);
 
uint8_t mmhal_wlan_spi_rw(uint8_t data);
 
void mmhal_wlan_spi_read_buf(uint8_t *buf, unsigned len);
 
void mmhal_wlan_spi_write_buf(const uint8_t *buf, unsigned len);
 
void mmhal_wlan_hard_reset(void);
 
bool mmhal_wlan_ext_xtal_init_is_required(void);
 
void mmhal_wlan_send_training_seq(void);
 
void mmhal_wlan_register_spi_irq_handler(mmhal_irq_handler_t handler);
 
void mmhal_wlan_set_spi_irq_enabled(bool enabled);
 
bool mmhal_wlan_spi_irq_is_asserted(void);
 
void mmhal_wlan_clear_spi_irq(void);
 
typedef void (*mmhal_wlan_pktmem_tx_flow_control_cb_t)(void);
 
struct mmhal_wlan_pktmem_init_args
{
    mmhal_wlan_pktmem_tx_flow_control_cb_t tx_flow_control_cb;
};
 
void mmhal_wlan_pktmem_init(struct mmhal_wlan_pktmem_init_args *args);
 
void mmhal_wlan_pktmem_deinit(void);
 
enum mmwlan_tx_flow_control_state mmhal_wlan_pktmem_tx_flow_control_state(void);
 
enum mmhal_wlan_pkt_class
{
    MMHAL_WLAN_PKT_DATA_TID0,       
    MMHAL_WLAN_PKT_DATA_TID1,       
    MMHAL_WLAN_PKT_DATA_TID2,       
    MMHAL_WLAN_PKT_DATA_TID3,       
    MMHAL_WLAN_PKT_DATA_TID4,       
    MMHAL_WLAN_PKT_DATA_TID5,       
    MMHAL_WLAN_PKT_DATA_TID6,       
    MMHAL_WLAN_PKT_DATA_TID7,       
    MMHAL_WLAN_PKT_MANAGEMENT,      
    MMHAL_WLAN_PKT_COMMAND,         
};
 
struct mmpkt *mmhal_wlan_alloc_mmpkt_for_tx(uint8_t pkt_class,
                                            uint32_t space_at_start, uint32_t space_at_end,
                                            uint32_t metadata_length);
 
struct mmpkt *mmhal_wlan_alloc_mmpkt_for_rx(uint8_t pkt_class,
                                            uint32_t capacity, uint32_t metadata_length);
 
#define MMHAL_WLAN_MMPKT_TX_MAX_SIZE    (1664)
 
#define MMHAL_WLAN_MMPKT_RX_MAX_SIZE    (1668)
 
#ifndef MMPKTMEM_TX_POOL_N_BLOCKS
#define MMPKTMEM_TX_POOL_N_BLOCKS       (20)
#endif
 
#ifndef MMPKTMEM_RX_POOL_N_BLOCKS
#define MMPKTMEM_RX_POOL_N_BLOCKS       (23)
#endif
 
 
enum mmhal_sdio_error_codes
{
    MMHAL_SDIO_INVALID_ARGUMENT = -1,
    MMHAL_SDIO_HW_ERROR = -2,
    MMHAL_SDIO_CMD_TIMEOUT = -3,
    MMHAL_SDIO_CMD_CRC_ERROR = -4,
    MMHAL_SDIO_DATA_TIMEOUT = -5,
    MMHAL_SDIO_DATA_CRC_ERROR = -6,
    MMHAL_SDIO_DATA_UNDERFLOW = -7,
    MMHAL_SDIO_DATA_OVERRUN = -8,
    MMHAL_SDIO_OTHER_ERROR = -9,
};
 
int mmhal_wlan_sdio_startup(void);
 
int mmhal_wlan_sdio_cmd(uint8_t cmd_idx, uint32_t arg, uint32_t *rsp);
 
struct mmhal_wlan_sdio_cmd53_write_args
{
    uint32_t sdio_arg;
    const uint8_t *data;
    uint16_t transfer_length;
    uint16_t block_size;
};
 
int mmhal_wlan_sdio_cmd53_write(const struct mmhal_wlan_sdio_cmd53_write_args *args);
 
struct mmhal_wlan_sdio_cmd53_read_args
{
    uint32_t sdio_arg;
    uint8_t *data;
    uint16_t transfer_length;
    uint16_t block_size;
};
 
int mmhal_wlan_sdio_cmd53_read(const struct mmhal_wlan_sdio_cmd53_read_args *args);
 
 
/*
 * SDIO argument definition, per SDIO Specification Version 4.10, Part E1, Section 5.3.
 */
 
enum mmhal_sdio_rw
{
    MMHAL_SDIO_READ  = 0,               
    MMHAL_SDIO_WRITE = (1ul << 31),     
};
 
enum mmhal_sdio_function
{
    MMHAL_SDIO_FUNCTION_0 = 0,              
    MMHAL_SDIO_FUNCTION_1 = (1ul << 28),    
    MMHAL_SDIO_FUNCTION_2 = (2ul << 28),    
};
 
enum mmhal_sdio_mode
{
    MMHAL_SDIO_MODE_BYTE = 0,               
    MMHAL_SDIO_MODE_BLOCK = (1ul << 27),    
};
 
enum mmhal_sdio_opcode
{
    MMHAL_SDIO_OPCODE_FIXED_ADDR = 0,
    MMHAL_SDIO_OPCODE_INC_ADDR   = (1ul << 26),
};
 
#define MMHAL_SDIO_ADDRESS_OFFSET (9)
#define MMHAL_SDIO_ADDRESS_MAX    ((1ul << 18) - 1)
 
#define MMHAL_SDIO_COUNT_OFFSET   (0)
#define MMHAL_SDIO_COUNT_MAX      ((1ul << 10) - 1)
 
#define MMHAL_SDIO_CMD52_DATA_OFFSET  (0)
 
static inline uint32_t mmhal_make_cmd52_arg(enum mmhal_sdio_rw rw, enum mmhal_sdio_function fn,
                                            uint32_t address, uint8_t write_data)
{
    uint32_t arg;
 
    arg = rw | fn;
    arg |= (address << MMHAL_SDIO_ADDRESS_OFFSET);
    arg |= (write_data << MMHAL_SDIO_CMD52_DATA_OFFSET);
    return arg;
}
 
static inline uint32_t mmhal_make_cmd53_arg(enum mmhal_sdio_rw rw, enum mmhal_sdio_function fn,
                                            enum mmhal_sdio_mode mode, uint32_t address,
                                            uint16_t count)
{
    uint32_t arg;
 
    arg = rw | fn | MMHAL_SDIO_OPCODE_INC_ADDR | mode;
    arg |= (address << MMHAL_SDIO_ADDRESS_OFFSET);
    arg |= (count << MMHAL_SDIO_COUNT_OFFSET);
    return arg;
}
 
#ifdef __cplusplus
}
#endif